ACUMOD[TM] software automatically converts ACUGEN Software's ATGEN[TM] model files into Verilog format simulation models. This product, when used in conjunction with ATGEN test generation software, allows conversion of raw PLD JEDEC files or FPGA netlists into VERILOG models.
Great for Functional Board Test Simulations
Successful functional board test programs require mountains of diagnostic data (either for guided probe or fault dictionary). Whole-board Verilog simulation is one method for producing diagnostic data as part of a functional board test program. However, Verilog simulators need models for all devices on the board, which usually include a multitude of PLDs. Since every PLD design is different, users need to create a new model for each PLD design on the board.
Creating and verifying models is laborious and time consuming, so the most cost effective solution is to use our ACUMOD product to generate the models automatically from the JEDEC file. If the designer changes the design, just rerun the ACUMOD program --it is as simple as that!
Great for Design Verification
Sometimes a whole-board simulation is the best way to verify your design logic and check for unexpected device interactions. Here again, you need to have simulation models for all devices on the board, including the PLDs. This ACUMOD program automatically generates these models for Verilog simulators.
Accurate Timing Available
Accurate timing is most valuable in timing verification and applications that do guided probe diagnosis at clock-rate. The ACUMOD product includes timing data on thousands of PLDs, organized by PLD manufacturer order part numbers. Timing data includes primarily delay information, not pulse width, frequency, setup, hold and other margins. Some devices in our library do not have timing modeled -- timing can be added on request.
ACUMOD software must be run on a computer that has an ATGEN base product installed. ACUMOD supports whatever models are installed with the ATGEN base product.
Technical Support Service and Updates
Technical Support is provided under the support plan for your particular ATGEN base product.
Easy to Use
The translator is invoked by typing "ACUMOD" and operating a menu/fill-in-the-form interface that helps you choose the right device part numbers. For JEDEC-based models, customers can create new timing variants (i.e. new speed grade) by providing an ASCII file in an intuitive format.
A sample for a 22V10 is shown here:
/* * AmPALCE22V10 * Source: AMD PAL Data Book 1990, 2-247 * Commercial * 5-jan-91 */ tsu = 8.0e-9; tw = 5.0e-9; twl = 5.0e-9; twh = 5.0e-9; tpd = 10.0e-9; tclk= 6.0e-9; /* tCO */ tco = 12.5e-9; tea = 10.0e-9; ter = 10.0e-9; tap = 15.0e-9; tar = 8.0e-9; fmax= 71.0e6;
Wide Range of PLD Types
ACUMOD supports all PLD types supported by ATGEN software. All popular FPGA families are supported based on netlists produced by their design tools as summarized in the table below:
|Actel||reads .adl, .pin, and .del files|| timing from .del |
|Altera MAX||reads .edo or .rtp and .fit|| siming from .edo |
|Lattice ispLSI||reads .sim|| timing from .sim |
|Lucent ORCA||reads .edn|| no timing yet |
|QuickLogic||reads .edo|| timing from .edo |
|Xilinx||reads .edn|| no timing yet|
The complete list of JEDEC-based models at the time this document was printed is:
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