Pin Fault Testing

Effective in-circuit board testing depends on high pin fault coverage to catch common board assembly defects. Knowing your actual pin fault coverage, in turn, depends on accurate fault coverage measurement. Accurate fault coverage measurement allows you to improve your process and know when you have reached your goal. This paper discusses pin fault coverage measurement, focusing on common mistakes such as ignoring faults on input pins, or using a "node exercise" method.

What is a PIN?

A pin is the metal external leg of an integrated circuit (IC). The pin connects the Programmable Logic Device (PLD) or other type of IC to a circuit board and other devices.

What is a FAULT?

A fault is a manufacturing defect which can cause the circuit to malfunction or fail. In-circuit board test operations are intended to detect circuit board assembly defects, typically bent, broken (open), or shorted device pins.


Fault coverage is the percentage of total faults detected by the test. To determine fault coverage you need to know how many faults your particular PLD has. To calculate the number of hardware pin faults for a PLD: subtract the power, ground, and no-connect pins, and multiply the remaining number of pins by two. For example, a XilinxTM LCATM, in an 84-pin grid array package with 4 power & ground pins has a total of 160 pin faults: 80 stuck-at-one faults, and 80 stuck-at-zero faults. If the LCA has bi-directional pins, the number of faults will be even higher. A bi-directional pin has faults associated with it as an input, an output and in relation to the high impedance tristate driver. For our example, we will assume the pins are fixed as either inputs or outputs. Your fault coverage is determined by the number of these fault locations your test detects. This number is usually shown as a percentage to make it easy to understand. The closer the percentage is to 100% the better the test.

Why are PIN FAULTS important?

The pins of a PLD can become "stuck" in any number of ways. Perhaps the pin gets bent while being inserted into the circuit board; or the pin gets accidentally soldered to another pin, to the power plane, or to the ground plane. Maybe the device gets damaged internally causing the pin to be defective. The number of ways a PLD can become damaged is virtually limitless! Most electronic systems manufacturers perform a high coverage pin fault test on each device of a circuit board after assembly. In-circuit board testing catches the majority of bad PLDs and other components before they get out the door and into the hands of customers.

How do I know if my test has High PIN FAULT coverage?

The difficulty comes in knowing if the test you are using on your PLD has "high pin fault coverage." Some people use the "node exercise count" method to check for pin faults. Using this technique you check that each input pin, output pin, and possibly some internal nodes on your PLD were able to reach a logical high and logical low. If all the nodes reach both the high and low states the test is labeled "GOOD". But it is ONLY a good test if you want to check for OUTPUT pins faults only. The "node exercise count" method cannot tell if you have detected any INPUT pin faults. Please note that even some "stuck at" fault detection techniques don’t check for input pin faults. To understand a coverage number, you need to know whether it was based on a "node exercise" or "stuck-at" method. You also need to examine a fault list and match each fault with its location in the circuit.

How do I detect PIN FAULTS?

When simulating stuck-at faults, a faulty location can fail in one of two ways. A "stuck-at-one" causes the location to simulate as a logic one, or high, value for the entire test. Similarly, a "stuck-at-zero" causes the location to simulate as a logic zero, or low, value for the entire test.

To check a pin to see if it is "stuck-at-one" or "stuck-at-zero" you need to check if it can reach the state opposite of the fault. An output pin has to drive a logical low to detect a stuck-at-one fault, and drive to a logical high to detect a stuck-at-zero fault. Input pins are trickier. To be sure you have detected a stuck-at-one or stuck-at-zero input pin, an output pin must change state as a result of the input being toggled. Let's look at the following diagram:

Undisplayed Graphic

In this case, the "node exercise" would count pin 2 as having been "exercised" in both states. However, in reality, pin 2 has no effect on this circuit at all. The toggle on pin 2 is masked by pin 1 being held low. For an AND gate, the output, pin 3, stays low because an input, pin 1, is held low. To detect an input pin fault on pin 2, you need pin 1 held high so the effects of pin 2’s toggle will be seen on output pin 3. For circuits more complex than an AND gate, detection of input pin faults is more difficult, making a "node exercise" measure even less meaningful.

An example

Now let's look at some numbers. In our example, we had a Xilinx LCA with 84 pins (80 functional pins). Let's assume that half of them are inputs and half of them are outputs. Each pin has two faults for a total of 160 faults. If 35 of the 40 output pins reach a logic high and a logic low, we detected 70 of 160 faults, or only 44% of the possible pin faults!!! Some of the input faults will also be captured because the inputs get stimulated so the outputs will toggle. But if we don’t check, we won’t know if we detected 5% or 45% of the input pin faults. This means our test coverage could be only 50% or less depending on the design in the PLD.

Can PIN FAULT testing save me money?

Let's do a comparison of three different testing scenarios:

(1) No Test;

(2) PIN Fault coverage rate of 50%;

(3) and, the 99% PIN Fault coverage typical of ATGEN test generation.

For the comparison let's make some approximations. First, we will set the price of allowing a "bad" board to get through your system at $500. Included in this approximation is the cost of the board itself, the cost of customer service call(s), the cost of diagnosis, and the cost of a tarnished reputation.

A second approximation must be the insertion failure rate for the device we are testing. The number we will use is 1%. This means that we assume 1% of the boards under test will have pin faults.

Now we are ready to compare.

If you don't test at all (NO TEST), and 1% of your boards are "bad" then you are losing $5 for every board you make.

If you have a test that detects 50% of the "bad" boards, you can save $5 X 50% or $2.50. Savings is better than cost but you can still do better.

If your test can detect 99% of the "bad" boards, you will save $5 X 99% = $4.95 per board. Depending on how many boards your company processes, a comprehensive PIN Fault coverage test can make significant savings a real possibility for your in-circuit testing process.

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